Trench isolation techniques may be used in the fabrication of semiconductor devices to address what is commonly referred to as “bird's beak” associated with conventional local oxidation of silicon (LOCOS) processes. For example, trench isolation techniques can be used to provide isolation and insulation structures between circuits to define an active region. As the level of integration in semiconductor devices increases, trench widths may be decreased, which may increase the aspect ratio of the trenches. High aspect ratio trenches may be difficult to fill without forming voids.
FIGS. 1 to 3 are sectional views illustrating a method of forming a conventional trench isolation layer. Referring to FIG. 1, a pad oxide layer and a pad nitride layer can be sequentially formed on a semiconductor substrate 1. The pad nitride layer and the pad oxide layer may be sequentially patterned, thereby forming a pad oxide layer pattern 3 and a pad nitride layer pattern 5 exposing a predetermined portion of the semiconductor substrate.
Using the pad nitride layer pattern 5 as an etch mask, the exposed semiconductor substrate 1 may be etched, thereby forming a trench defining an active region. A thermal oxide layer (not shown) and a silicon nitride layer (not shown) may be sequentially formed on inner walls of the trench. Then, a trench isolation layer 13 filling the trench can be formed on the overall surface of the semiconductor substrate 1 having the silicon nitride layer. The trench isolation layer 13 can be formed using a high density plasma chemical vapor deposition (HDPCVD) technique. The HDPCVD technique can include a deposition process and a sputtering etch process, which may be alternately and repeatedly performed. In the deposition process, an oxide layer can be formed on a bottom and sidewalls of the trench. In the sputtering etch process, the oxide layer can be sputtered and portions thereof removed (or peeled off) from the sidewalls of the trench. As shown in FIG. 1, if the width W1 of the trench is relatively wide, the oxide layer deposited on the opposite sidewalls can be uniformly formed on the overall sidewalls.
Referring to FIG. 2, a trench is formed with a relatively narrow width W2 in order to increase the level of integration of the semiconductor device. The trench having the width W2 has a higher aspect ratio relative to the trench having the width W1. In forming the trench of FIG. 2, the oxide layer can be sputtered and peeled off from an upper portion A of a sidewall of the trench (during the sputtering etch process) but may be deposited again on an upper portion B of the opposite sidewall. In the same way, the oxide layer sputtered and peeled off from portion B can be deposited on the portion A. As a result, an overhang phenomenon may occur, in which the upper portion of the trench becomes narrower than the lower portion thereof.
Referring to FIG. 3, in the case of forming the trench isolation layer 13 on the trench having the narrow width W2 using the HDPCVD technique, the upper sidewalls of the trench meet before the lower portions of the trench are filled because the sputtered oxide layer is re-deposited on the opposing upper portions A/B of the sidewalls. As a result, the trench isolation layer 13, inside the trench having the narrow width W2, may be formed with a void, which may deteriorate the insulation characteristics of the trench isolation layer.
Another method of forming a trench isolation layer is discussed in U.S. Pat. No. 6,737,333 B2, entitled Semiconductor Device Isolation Structure And Method Of Forming to Chen, et. al. According to Chen, et. al, a first oxide layer pattern and a hard mask pattern are sequentially formed on a semiconductor substrate. Using the first oxide layer pattern and the hard mask pattern as etch masks, the semiconductor substrate is etched, thereby forming a trench. A second oxide layer is formed to cover inner walls of the trench. A spin-on-glass (SOG) layer is formed inside the trench having the second oxide layer. The SOG layer is etched, to recess the SOG layer below a surface of the semiconductor substrate. A third oxide layer is formed on the recessed SOG layer.
The second oxide layer can be formed using a thermal oxidation technique, a chemical vapor deposition technique, a high density plasma chemical vapor deposition technique or an atomic layer deposition technique. The high density plasma chemical vapor deposition technique may be used because of its advantage of mass production, but the overhang phenomenon discussed may occur when this approach is used to form materials in trenches having high aspect ratios as described in reference to FIG. 2. Further, the SOG layer may be formed by coating the semiconductor substrate with an SOG material to fill the inside of the trench having the second oxide layer. The overhang phenomenon may interfere with the flow of the SOG material during the coating process. That is, when the upper portion of the second oxide layer protrudes due to the overhang phenomenon, it may be difficult to completely fill the inside of the trench with the SOG material. Further, the SOG material may be classified into an organic SOG material and an inorganic SOG material, and has various kinds. The electrical characteristics of SOG layers may vary widely depending on the type of SOG material used.